Exemplary embodiments relate to a nonvolatile memory device and a method of operating the same, and, more particularly, to a page buffer.
FIG. 1 is a circuit diagram showing a known page buffer.
The page buffer includes a bit line selector 11, a bit line transmission circuit 12, a precharge circuit 13, a data transmission circuit 14, a latch circuit 15, a set/reset circuit 16, a data I/O circuit 17, and a discharge circuit 18.
The bit line selector 11 is used to select a bit line BL coupled to a memory cell array (not shown).
The bit line transmission circuit 12 electrically couples a sense node SO and the bit line BL, selected by the bit line selector 11, in response to a bit line transmission signal BLCLAMP. The bit line transmission circuit 12 comprises an NMOS transistor T1 operated in response to the bit line transmission signal BLCLAMP.
The precharge circuit 13 transfers power supply voltage Vcc to the sense node SO in response to a precharge signal PRECHb. The precharge circuit 13 is coupled between a terminal for the power supply voltage Vcc and the sense node SO, and comprises a PMOS transistor T2 operated in response a precharge signal PRECHb.
The data transmission circuit 14 transfers a certain voltage based on data stored in the latch circuit 15 to the sense node SO, or transfers data, stored in the latch circuit 15, to different latches. Each of the latches is formed of a pair of inverters. The latch circuit 15 includes a plurality of latches for storing data. Accordingly, in order to transfer the data of the plurality of latches to the sense node SO, the data transmission circuit 14 includes a plurality of switch devices T3 to T10. The switch devices T3 to T10 comprise respective NMOS transistors operated in response to respective switch signals S3 to S10.
The set/reset circuit 16 sets or resets the latches of the latch circuit 15, and includes a plurality of NMOS transistors T11 to T18 coupled between a common source CON and the respective latches of the latch circuit 15. The NMOS transistors T12, T14, T16, and T18 for setting the latches are operated in response to respective set signals CSET, MSET, TSET, and FSET. Voltage levels of respective nodes QC, QM, QT, and QF of the latches are determined in response to the respective set signals CSET, MSET, TSET, and FSET. The NMOS transistors T11, T13, T15, and T17 for resetting the latches are operated in response to respective reset signals CRST, MRST, TRST, and FRST. Voltage levels of respective nodes QC_N, QM_N, QT_N, and QF_N of the nodes are determined in response to respective reset signals CRST, MRST, TRST, and FRST.
The data I/O circuit 17 is coupled to any one of the latches of the latch circuit 15 and is configured to input data to the relevant latch or externally output data of the relevant latch. If the data I/O circuit 17 is coupled to the latch including the node QC and the node QC_N, the data I/O circuit 17 includes an NMOS transistor T20 for coupling the node QC and a data line DL and an NMOS transistor T21 for coupling the node QC_N and a data line DL/, in response to an I/O signal CS.
The discharge circuit 18 comprises an NMOS transistor T19 coupled between the common node CON and a ground terminal Vss, and configured to discharge the common node CON in response to a voltage level of the sense node SO.
Meanwhile, with an increase in the number of transistors of a page buffer, the number of signals for operating the transistors also increases, and thus a method of operating the page buffer may become complicated. Furthermore, the size of a nonvolatile memory device may increase with an increase in the number of transistors.